module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);

    reg [3:0]   state;
    reg [3:0]   nxt_state;

    wire        w_shft_ena;
    reg[1:0]    w_cntr;
    localparam A = 0;
    localparam B = 1;
    localparam B1 = 2;
    localparam B2 = 4;

    // State transition logic (combinational)
    always @(*) begin
        case (state)
            A:begin
                if(s)
                    nxt_state = B;
                else
                    nxt_state = A;
            end
            B:begin
                nxt_state = B1;
            end
            B1:begin
                nxt_state = B2;
            end
            B2:begin
                nxt_state = B;
            end
          default: begin
            nxt_state = A;
          end
        endcase
    end

    // State flip-flops (sequential)
    always @(posedge clk ) begin
        if(reset)
            state   <=  A;
        else begin
            state   <=  nxt_state;
        end  
    end

    always @(posedge clk ) begin
        if(reset)
            w_cntr   <=  2'b0;
        else if(state == B)begin
            w_cntr   <=  w;
        end
        else if(state == B1 || state == B2)begin
            w_cntr   <=  w_cntr + w;
        end   
    end

    assign  z    =   state == B &&  w_cntr == 2 ? 1'b1 : 1'b0;

endmodule
